1. Field of the Invention
The present invention relates to the field of display technology, and in particular to a method for manufacturing an active matrix organic light emitting diode (AMOLED) backplane and a structure thereof.
2. The Related Arts
In the field of display technology, the flat panel display technology, including liquid crystal display (LCD) and organic light emitting diode (OLED), has gradually taken the place of cathode ray tube (CRT) displays. Among them, OLED has various advantages, including self-luminous, low drive voltage, high emission efficiency, short response time, high sharpness and contrast, approximately 180 degree view angle, wide range of operation temperature, and being capable of achieving flexible displaying and large-area full-color displaying, and is widely used in for example mobile phone screens, computer displays, and full-color televisions and are considered a display device of the most prosperous development.
According to the types of driving, OLEDs can be classified as passive OLEDs (such as PMIOLEDs) and active OLEDs (such as AMOLEDs). An AMOLDE is a self-luminous device composed of a low temperature poly-silicon (LTPS) driving backplane and an electroluminescent layer. The LTPS possesses relatively high electron mobility and for an AMOLED, which involves the LTPS material, various advantages, such as high resolution, high response speed, high brightness, high aperture ratio, and low power consumption, can be achieved.
FIG. 1 is a cross-sectional view showing a conventional active matrix organic light emitting diode (AMOLED) backplane. A method for manufacturing the AMOLED backplane generally comprises the following steps:
Step 1: providing a substrate 100, wherein the substrate 100 comprises a switch thin-film transistor (TFT) zone, a storage capacitor zone, and a drive TFT zone, and depositing a buffer layer 200 on the substrate 100;
Step 2: depositing an amorphous silicon layer on the buffer layer 200, conducting a crystallization process to crystallize and convert the amorphous silicon layer into a poly-silicon layer, and conducting a masking operation to subject the poly-silicon layer to patternization so as to form a first poly-silicon section 310 located in the switch TFT zone, a second poly-silicon section 320 located in the drive TFT zone, and a third poly-silicon section 330 located in the storage capacitor zone;
Step 3: depositing a gate insulation layer 400 on the first poly-silicon section 310, the second poly-silicon section 320, the third poly-silicon section 330, and the buffer layer 200;
Step 4: depositing a first photoresist layer on the gate insulation layer 400 and conducting a masking operation to patternize the first photoresist layer,
wherein the first photoresist layer shields middle portions of the first poly-silicon section 310 and the second poly-silicon section 320 but does not shield the third poly-silicon section 330; and
with the first photoresist layer serving as a shielding layer, P-type heavy doping is applied to the first poly-silicon section 310, the second poly-silicon section 320, and the third poly-silicon section 330 so as to form P-type heavily doped zones respectively on two sides of each of the first poly-silicon section 310 and the second poly-silicon section 320 and the entirety of the third poly-silicon section 330;
Step 5: removing the first photoresist layer, depositing a first metal layer on the gate insulation layer 400, and conducting a masking operation to patternize the first metal layer so as to form a first gate terminal 610 in the switch TFT zone, a second gate terminal 620 in the drive TFT zone, and a metal electrode 630 in the storage capacitor zone;
Step 6: depositing an interlayer insulation layer 700 on the first gate terminal 610, the second gate terminal 620, the metal electrode 630, and the gate insulation layer 400 and conducting a masking operation to form first vias 710 in the interlayer insulation layer 700 and the gate insulation layer 400 to respectively correspond to the P-type heavily doped zones on the two sides of the first poly-silicon section 310 and those of the second poly-silicon section 320;
Step 7: depositing a second metal layer on the interlayer insulation layer 700 and conducting a masking operation to patternize the second metal layer so as to form first source/drain terminals 810 and second source/drain terminals 820,
wherein the first source/drain terminals 810 and the second source/drain terminals 820 are respectively connected through the first vias 710 to the P-type heavily doped zones on the two sides of the first poly-silicon section 310 and those of the second poly-silicon section 320;
Step 8: forming a planarization layer 830 on the first source/drain terminals 810, the second source/drain terminals 820, and the interlayer insulation layer 700 and conducting a masking operation to form a second via 840 in the planarization layer 830 to correspond to the second source/drain terminals 820;
Step 9: depositing a conductive film on the planarization layer 830 and conducting a masking operation to patternize the conductive film so as to form an anode 850,
wherein the anode 850 is connected through the second via 840 to the second source/drain terminals 820;
Step 10: depositing a second photoresist layer on the anode 850 and the planarization layer 830 and conducting a masking operation to patternize the second photoresist layer so as to form a pixel definition layer 900; and
Step 11: depositing a third photoresist layer on the pixel definition layer 900 and the anode 850 and conducting a masking operation to patternize the third photoresist layer so as to form photo spacers 910.
Such a process requires nine masks and thus the process is complicated and has low manufacturing efficiency and high cost. Therefore, it is desired to provide a novel method for manufacturing an AMOLED backplane and a structure thereof that overcomes the above problems.